The present invention relates to integrated circuit devices having through-silicon vias, and more particularly to a technique for reclaiming usable integrated circuit chip area near through-silicon vias.
It has long been known that semiconductor materials such as silicon and germanium exhibit the piezoresistance effect (mechanical stress-induced changes in electrical resistance). See for example C. S. Smith, “Piezoresistance effect in germanium and silicon”, Phys. Rev., vol. 94, pp. 42-49 (1954), incorporated by reference herein. The piezoresistance effect has formed the basis for certain kinds of pressure sensors and strain gauges, but only recently has it received attention in the manufacture of integrated circuits.
Methods have been developed to model the impact of stress on the behavior of integrated circuit devices at the level of individual transistors. These methods include, for example, full-scale analysis with a Technology Computer Aided Design (TCAD) system; and a method described in U.S. patent application Ser. No. 11/291,294, filed Dec. 1, 2005, Docket No. SYNP 0693-1, incorporated herein by reference.
Behaviors characterized by the various methods for analyzing stress impact at the level of individual transistors can be used to derive circuit level parameters (e.g. SPICE parameters) of the device for subsequent analysis of the circuit at macroscopic levels. Such analysis can help predict whether the circuit will operate as intended, and with what margins, or whether the design or layout needs to be revised. For transistors affected by stress caused by shallow trench isolation (STI) regions in proximity to transistor channel regions, revisions can often be made by applying certain general rules-of-thumb, such as increasing the width of any transistor that, according to the stress analysis, turns out to be weaker than expected. Other techniques can also be used to relax known undesirable stress, to introduce known desirable stress, or merely to improve uniformity throughout the layout. See U.S. Patent Publication No. 2007-0202663, Docket No. SYNP 0858-1, incorporated herein by reference.
As integrated circuit scaling becomes increasingly difficult with each technology node, three-dimensional (3D) integration technologies have emerged as viable alternatives to achieve the requisite integration densities. 3D integration improves system performance and allows heterogeneous integration of circuit blocks. Many 3D integration techniques include vertical interconnects using through-silicon vias (TSVs). These structures are complex geometries consisting of various materials with widely varying mechanical properties. During the manufacturing process, these geometries undergo thermal cycling that introduces thermo-mechanical stresses in the surrounding silicon. The TSVs also introduce thermal mismatch stresses in the active silicon and affect the carrier mobility. These stresses alter the electron and hole mobilities near the TSV, thereby introducing undesirable transistor variations.
A typical response to these stresses is to define an exclusion zone around them, and to avoid placing transistors within the exclusion zones. For a typical 5 um diameter TSV, the exclusion zone can be as large as 5-10 um wide, which translates into an unusable area for each TSV of 180 to 500 um2. With a roadmap predicting around 10,000 TSVs per chip, this adds up to an enormous 1.8 mm2-5 mm2 of otherwise usable space per chip that is lost due to the use of TSVs. It would be highly desirable to find ways of reclaiming some of that area so that it can be used beneficially.